EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 78

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Overview
4–4
Stratix III Device Handbook, Volume 1
The default value for the byte enable signals is high (enabled), in which
case writing is controlled only by the write enable signals. The byte
enable registers have no clear port. When using parity bits on the M9K
and M144K blocks, the byte enable controls all nine bits (eight bits of data
plus one parity bit). When using parity bits on the MLAB, the byte-enable
controls all 10 bits in the widest mode.
Byte enables operate in a one-hot fashion, with the least significant bit
(LSB) of the byteena signal corresponding to the least significant byte of
the data bus. For example, if using a RAM block in ×18 mode, with
byteena = 01, data[8..0] is enabled and data[17..9] is disabled.
Similarly, if byteena = 11, both data[8..0] and data[17..9] are
enabled. Byte enables are active high.
1
Figure 4–1
(byteena) signals control the operations of the RAM.
When a byte-enable bit is de-asserted during a write cycle, the
corresponding data byte output can appear as either a “don't care” value
or the current data at that location. The output value for the masked byte
is controllable via the Quartus II software. When a byte-enable bit is
asserted during a write cycle, the corresponding data byte output also
depends on the setting chosen in the Quartus II software.
You cannot use the byte enable feature when using the error
correction coding (ECC) feature on M144K blocks.
shows how the write enable (wren) and byte enable
Altera Corporation
November 2007