EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 179

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–20. Stratix III PLL Ports
Notes to
(1)
(2)
Altera Corporation
November 2007
inclk0
inclk1
fbin
Table 6–12. PLL Input Signals (Part 1 of 2)
You can feed the inclk0 or inclk1 clock input from any one of four dedicated clock pins located on the same side
of the device as the PLL.
You can drive to global or regional clock networks or dedicated external clock output pins. n = 6 for Left/Right PLLs
and n = 9 for Top/Bottom PLLs.
Port
Figure
6–20:
Input clock to the PLL
Input clock to the PLL
Compensation feedback input to
the PLL
inclk0 (1)
inclk1 (1)
fbin
clkswitch
areset
pfdena
scanclk
scandata
scanclkena
configupdate
phasecounterselect[3..0]
phaseupdown
phasestep
Table 6–12
Description
shows the PLL input signals for Stratix III devices.
scandataout
clkbad[1..0]
(2) clk[n..0]
phasedone
activeclock
Dedicated pin, adjacent
PLL, GCLK, or RCLK
network
Dedicated pin, adjacent
PLL, GCLK, or RCLK
network
Pin or GCLK, RCLK,
LVSDCLK
scandone
locked
fbout
Clock Networks and PLLs in Stratix III Devices
Source
Stratix III Device Handbook, Volume 1
Signal Driven by Internal Logic
internal logic or I/O pins
N
N
PFD
Internal Clock Signal
counter
counter
Signal driven to
Destination
Physical Pin
6–29