EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 317

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Introduction
Altera Corporation
November 2007
SIII51009-1.3
The Stratix
capabilities to support source-synchronous communication protocols
such as Utopia, Rapid I/O™, XSBI, SGMII, SFI, and SPI.
Stratix III devices have the following dedicated circuitry for high-speed
differential I/O support:
■
■
■
■
■
■
■
For high-speed differential interfaces, Stratix III devices support the
following differential I/O standards:
■
■
■
■
■
HSTL and SSTL I/O standards can be used only for PLL clock inputs and
outputs in differential mode.
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
Dynamic phase aligner (DPA)
Synchronizer (FIFO buffer)
Analog PLLs (located on left and right sides of the device)
Low voltage differential signaling (LVDS)
Mini-LVDS
Reduced swing differential signaling (RSDS)
HSTL
SSTL
®
III device family offers up to 1.25-Gbps differential I/O
9. High-Speed Differential I/O
Interfaces and DPA in
Stratix III Devices
9–1