EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 332

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clocking
Figure 9–14. LVDS/DPA Clocks in Stratix III Devices with Center and Corner PLLs
9–16
Stratix III Device Handbook, Volume 1
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LVDS
Clock
LVDS
Clock
PLL_L2
PLL_L3
PLL_L4
Center
Center
Corner
PLL_L1
Corner
Clock
Clock
DPA
DPA
Source-Synchronous Timing Budget
This section discusses the timing budget, waveforms, and specifications
for source-synchronous signaling in Stratix III devices. LVDS I/O
standards enable high-speed data transmission. This high data
transmission rate results in better overall system performance. To take
advantage of fast system performance, it is important to understand how
to analyze timing for these high-speed signals. Timing analysis for the
differential block is different from traditional synchronous timing
analysis techniques.
Rather than focusing on clock-to-output and setup times, source
synchronous timing analysis is based on the skew between the data and
the clock signals. High-speed differential data transmission requires the
use of timing parameters provided by IC vendors and is strongly
influenced by board skew, cable skew, and clock jitter. This section
defines the source-synchronous differential data orientation timing
parameters, the timing budget definitions for Stratix III devices, and how
to use these timing parameters to determine a design’s maximum
performance.
Quadrant
Quadrant
Quadrant
Quadrant
Clock
Clock
DPA
DPA
PLL_R2
PLL_R3
PLL_R1
PLL_R4
Corner
Center
Center
Corner
LVDS
Clock
LVDS
Clock
Altera Corporation
November 2007
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