EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 49

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 2–12. Conditional Operation Example
Altera Corporation
October 2007
Carry Chain
syncdata
X[0]
X[1]
X[2]
Y[0]
Y[1]
Y[2]
The equation for this example is:
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract Y from X. If X is
less than Y, the carry_out signal is 1. The carry_out signal is fed to
an adder where it drives out to the LAB local interconnect. It then feeds
to the LAB-wide syncload signal. When asserted, syncload selects the
syncdata input. In this case, the data Y drives the syncdata inputs to the
registers. If X is greater than or equal to Y, the syncload signal is
de-asserted and X drives the data port of the registers.
The arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, add/subtract control, synchronous clear,
and synchronous load. The LAB local interconnect data inputs generate
the clock enable, counter enable, synchronous up/down, and
ALM 1
ALM 2
Comb &
Comb &
Comb &
Comb &
Adder
Adder
Adder
Adder
Logic
Logic
Logic
Logic
Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
X[2]
X[1]
X[0]
Adder output
is not used.
syncload
syncload
syncload
D
D
D
reg0
reg1
reg0
carry_out
Q
Q
Q
R[0]
R[1]
R[2]
Stratix III Device Handbook, Volume 1
To general or
local routing
To general or
local routing
To general or
local routing
To local routing &
then to LAB-wide
syncload
2–15