EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 449

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 13–6. IEEE Std. 1149.1 Timing Waveforms
Altera Corporation
November 2007
Captured
TMS
Driven
Signal
Signal
TDI
to Be
to Be
TDO
TCK
t
JCH
t
t
JSZX
done by holding TMS high for five TCK clock cycles, or by holding the
TRST pin low. Once in the TEST_LOGIC/RESET state, the TAP controller
remains in this state as long as TMS is held high (while TCK is clocked) or
TRST is held low.
Std. 1149.1 signals.
To start IEEE Std. 1149.1 operation, select an instruction mode by
advancing the TAP controller to the shift instruction register (SHIFT_IR)
state and shift in the appropriate instruction code on the TDI pin. The
waveform diagram in
code into the instruction register. It also shows the values of TCK, TMS,
TDI, TDO, and the states of the TAP controller. From the RESET state, TMS
is clocked with the pattern 01100 to advance the TAP controller to
SHIFT_IR.
JPZX
t
JCP
t
JSSU
t
JCL
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
t
JSH
Figure 13–6
t
t
JPCO
JSCO
Figure 13–7
t
JPSU
shows the timing requirements for the IEEE
represents the entry of the instruction
Stratix III Device Handbook, Volume 1
t
JPH
t
JSXZ
t
JPXZ
13–11