EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 300

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
8–30
Stratix III Device Handbook, Volume 1
f
however. The phase shifts on the DQS pins referenced by the same DLL
must all be a multiple of 22.5° (up to 90°), a multiple of 30° (up to 120°), a
multiple of 36° (up to 144°), or a multiple of 45° (up to 180°).
There are six different frequency modes for the Stratix III DLL, as shown
in
selections. In frequency mode 0, 1, and 2, the 6-bit DQS delay settings
vary with PVT to implement the phase-shift delay. In frequency modes 3,
4, and 5, only 5 bits of the DQS delay settings vary to implement the
phase-shift delay; the most significant bit of the DQS delay setting is set
to 0.
Refer to the
of the Stratix III Device Handbook for the frequency range of each mode.
For the 0° shift, the DQS signal bypasses both the DLL and the DQS logic
blocks. The Quartus II software will automatically set DQ input delay
chains so that the skew between the DQ and DQS pin at the DQ IOE
registers is negligible when the 0
DQS delay settings to the DQS logic block and the logic array.
The shifted DQS signal goes to the DQS bus to clock the IOE input
registers of the DQ pins. The signal can also go into the logic array for
resynchronization if you are not using the IOE resynchronization
registers. The shifted CQn signal can only go to the active-low input
register in the DQ IOE and is only used for QDRII+ and QDRII SRAM
interfaces.
Table 8–12. Stratix III DLL Frequency Modes
Frequency
Table
Mode
0
1
2
3
4
5
6
8–12. Each frequency mode provides different phase shift
DC and Switching Characteristics of Stratix III Devices
DQS Delay Setting
Bus Width
6 bits
6 bits
6 bits
6 bits
5 bits
5 bits
5 bits
o
shift is implemented. You can feed the
Available Phase Shift
22.5°, 45°, 67.5°, 90°
36°, 72°, 108°, 144°
45°, 90°, 135°, 180°
36°, 72°, 108°, 144°
45°, 90°, 135°, 180°
30°, 60°, 90°, 120°
30°, 60°, 90°, 120°
Altera Corporation
November 2007
Delay Chains
Number of
16
12
10
12
10
chapter
8
8