EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 234

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III I/O Structure
7–16
Stratix III Device Handbook, Volume 1
f
and input low voltage (V
specifications defined by EIA/JEDEC Standard JESD8-B with margin
when the Stratix III V
To ensure device reliability and proper operation, when interfacing with
a 3.3V I/O system using Stratix III devices, it is important to make sure
that the absolute maximum ratings of Stratix III devices are not violated.
Altera recommends performing IBIS simulation to determine that the
overshoot and undershoot voltages are within the guidelines.
When using the Stratix III device as a transmitter, some techniques can be
used to limit the overshoot and undershoot at the I/O pins, such as using
slow slew rate and series termination, but they are not required.
Transmission line effects that cause large voltage deviation at the receiver
are associated with impedance mismatch between the driver and
transmission line. By matching the impedance of the driver to the
characteristic impedance of the transmission line, overshoot voltage can
be significantly reduced. You can use a series termination resistor placed
physically close to the driver to match the total driver impedance to
transmission line impedance. Stratix III devices support series on-chip
termination (OCT) for all LVTTL/LVCMOS I/O standards in all I/O
banks.
When using the Stratix III device as a receiver, a technique you can use to
limit the overshoot, though not required, is using a clamping diode
(on-chip or off-chip). Stratix III devices provide an optional on-chip
PCI-clamp diode for column I/O pins. You can use this diode to protect
I/O pins against overshoot voltage.
Another method for limiting overshoot is reducing the bank supply
voltage (VCCIO) to 3.0 V. In this method, the clamp diode (on-chip or
off-chip), though not required, can sufficiently clamp overshoot voltage
to within the DC and AC input voltage specification. The clamped
voltage can be expressed as the sum of the supply voltage (V
diode forward voltage. By lowering V
overshoot and undershoot for all I/O standards, including 3.3-V
LVTTL/LVCMOS, 3.0-V LVTTL/LVCMOS and 3.0-V PCI/PCI-X.
Additionally, lowering V
Refer to the
in volume 2 of the Stratix III Device Handbook for more details about
absolute maximum rating and maximum allowed overshoot during
transitions.
DC and Switching Characteristics of Stratix III Devices
CCIO
CCIO
IL
voltage is powered by 3.3 V or 3.0 V.
) levels meet the 3.3-V I/O standards
to 3.0 V reduces power consumption.
CCIO
to 3.0 V you can reduce
Altera Corporation
November 2007
CCIO
) and the
chapter