EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 185

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Figure 6–23. Phase Relationship Between PLL Clocks in Normal Mode
Note to
(1)
Zero-Delay Buffer Mode
In zero-delay buffer (ZDB) mode, the external clock output pin is
phase-aligned with the clock input pin for zero delay through the device.
When using this mode, you must use the same I/O standard on the input
clocks and output clocks in order to guarantee clock alignment at the
input and output pins. This mode is supported on all Stratix III PLLs.
When using Stratix III PLLs in ZDB mode, along with single-ended I/O
standards, to ensure phase alignment between the clock input pin (CLK)
and the external clock output (CLKOUT) pin, you are required to
instantiate a bi-directional I/O pin in the design to serve as the feedback
path connecting the FBOUT and FBIN ports of the PLL. The PLL uses this
bi-directional I/O pin to mimic, and hence compensate for, the output
delay from the clock output port of the PLL to the external clock output
pin.
You cannot use differential I/O standards on the PLL clock input or
output pins when using ZDB mode.
1
Dedicated PLL Clock Outputs (1)
The external clock output can lead or lag the PLL internal clock signals.
Figure 6–24
Figure
Register Clock Port
The bi-directional I/O pin that you instantiate in your design
should always be assigned a single-ended I/O standard.
PLL Clock at the
PLL Reference
6–23:
Clock at the
shows ZDB mode implementation in Stratix III PLLs.
Input Pin
Phase Aligned
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
6–35