EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 377

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 11–6. FPP Configuration Timing Waveform
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
Altera Corporation
November 2007
t
t
t
t
t
t
t
Symbol
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
Table 11–5. FPP Timing Parameters for Stratix III Devices
You should use this timing waveform when the decompression and design security features are not used.
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix III device holds nSTATUS low for the time of the
Upon power-up, before and during configuration,
You should not leave DCLK floating after configuration. You should drive it high or low, whichever is more
convenient.
DATA[7..0] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose
pin settings.
CONF_DONE (4)
Figure
nSTATUS (3)
nCONFIG
nCONFIG
nCONFIG
nSTATUS
nCONFIG
nCONFIG
nSTATUS
INIT_DONE
DATA[7..0]
nCONFIG
User I/O
11–6:
DCLK
low to
low to
low pulse width
low pulse width
high to
high to first rising edge on
high to first rising edge of
t
t
CF2CD
CFG
Parameter
CONF_DONE
nSTATUS
t
nSTATUS
CF2ST1
t
Table 11–5
configuration when the decompression and the design security features
are not enabled.
CF2ST0
t
t
CF2CK
ST2CK
t
Byte 0 Byte 1 Byte 2 Byte 3
STATUS
High-Z
t
CH
t
CLK
low
t
DSU
high
t
CL
t
low
DH
defines the timing parameters for Stratix III devices for FPP
DCLK
DCLK
Notes
CONF_DONE
(1),
Minimum
Notes
(2)
100
10
—
—
—
2
2
is low.
Byte n
(1),
Stratix III Device Handbook, Volume 1
(2)
POR
(Part 1 of 2)
Maximum
Configuring Stratix III Devices
t
CD2UM
100
100
800
800
delay.
—
—
—
(3)
(3)
(5)
User Mode
User Mode
(5)
Units
ns
ns
μs
μs
μs
μs
μs
11–17