EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 479

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
October 2007
Note to
(1)
Bit
Description
Content
Table 15–2. Fault Injection Register
Bit[20] and Bit[19] cannot both be set to 1 as this is not a valid selection. The error detection circuitry will decode
it as no error injection.
Table
15–2:
Bit[20..19]
Error Type
Error Type
Bit[20]
0
1
0
Bit[19]
(1)
1
0
0
You can use Jam™ files (.jam) to automate the testing and verification
process. This is a powerful design feature that allows you to verify the
CRC functionality in-system, on the fly, without having to reconfigure
the device. You can then switch to the CRC circuit to check for real errors
induced by an SEU.
You can introduce a single error, double errors, or double errors adjacent
to each other to the configuration memory. This provides an extra way to
facilitate design verification and system fault tolerance characterization.
Use the JTAG fault injection register with EDERROR_INJECT instruction
to flip the readback bits. The Stratix III device is then forced into error test
mode.
The content of the JTAG fault injection register is not loaded into the fault
injection register during the processing of the last and the first frame. It is
only loaded at the end of this period.
1
Table 15–2
describes error injection.
1
Error Injection Type
Single byte error injection
double-adjacent byte error injection
no error injection
You can only introduce error injection in the first data frame, but
you can monitor the error information at any time. For more
information on the JTAG fault injection register and fault
injection register, refer to
page
After the test completes, Altera recommends that you
reconfigure the device.
shows how the fault injection register is implemented and
15–9.
“Error Detection Registers” on
Stratix III Device Handbook, Volume 1
Bit[18..8]
Byte Location of
the Injected Error
Depicts the
location of the
injected error in
the first data
frame.
SEU Mitigation in Stratix III Devices
Bit[7..0]
Error Byte Value
Depicts the
location of the bit
error and
corresponds to
the error injection
type selection.
15–5