EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 546

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–34
Stratix III Device Handbook, Volume 2
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5 V
1.8 V
1.5 V
1.2 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
SSTL-15 CLASS I
SSTL-15 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
1.2-V HSTL CLASS I
1.2-V HSTL CLASS II
Table 1–37. Maximum Input Toggle Rate on Stratix III Devices for Column I/O Pins (Part 1 of 2)
I/O Standard
VCCL=1.1V
Maximum I/O Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 1–37
Table 1–38
column I/O pins. Derating factors for maximum I/O toggle rates for
non-0pF loads will be published after characterization.
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
-2
specifies the maximum input toggle rates for column I/O pins.
specifies the maximum output toggle rates at 0pF load for
VCCL=1.1V
429
429
429
429
429
429
429
429
429
429
429
429
429
429
429
429
429
429
429
429
-3
VCCL=1.1V
367
367
367
367
367
367
367
367
367
367
367
367
367
367
367
367
367
367
367
367
-4
VCCL=1.1V
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
-4L
VCCL=0.9V
Altera Corporation
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
397
-4L
November 2007
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