EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 566

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–54
Stratix III Device Handbook, Volume 2
DIFFERENTIAL 2.5-V
SSTL CLASS I
DIFFERENTIAL 2.5-V
SSTL CLASS II
Table 1–42. Maximum Output Toggle Rate on Stratix III Devices for Dedicated Clock Output Pins (Part 6 of 6)
I/O Standard
OCT 50 Ω
OCT 25 Ω
OCT Setting
Strength or
Programmable IOE Delay
Table 1–43
Figure 7-8 in the Stratix III Device I/O Features chapter for annotation of
delays in the IOE.
Programmable Output Buffer Delay
Table 1–44
edge delays of the output buffer. Default delay is 0ps.
Current
D1
D2
D3
D4
D5
D6
D
Table 1–43. Stratix III IOE Programmable Delay
Table 1–44. Programmable Output Buffer Delay
OUTBUF
Parameter
Symbol
lists the delay chain settings that control the rising and falling
shows Stratix III IOE programmable delay settings. Refer to
VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V
400
350
-2
Available Settings
Rising and/or
Falling Edge delay
Parameter
16
15
16
343
300
8
8
7
-3
Minimum Delay
294
257
-4
0 (default)
Typical
(ps)
150
330
155
115
123
118
100
150
50
-2 Speed Grade
317
278
-4L
Altera Corporation
Maximum Delay
November 2007
Units
2581
(ps)
900
700
750
897
377
317
278
-4L
ps
ps
ps
ps
Units
MHz
MHz