EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 533

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
DPA jitter tolerance
SPI-4
Parallel Rapid I/O
Miscellaneous
Table 1–24. High Speed I/O Specifications for -2 Speed Grade
Table 1–25. DPA Lock Time Specifications - Preliminary
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following Left/Right PLL output frequency
specification: 150 MHz ≤ input clock frequency × W ≤ 1250 MHz.
The minimum specification is dependent on the clock source (PLL and clock pin, for example) and the clock routing
resource (global, regional, or local) utilized. The I/O differential buffer and input register do not have a minimum
toggle rate.
Pending silicon characterization.
Same as Device Clock tree f
Specifications for -3 and -4 speed grades will be available after silicon characterization.
Standard
Table
Symbol
1–24:
00000000001111111111
Training Pattern
Data channel peak-to-peak jitter tolerance
External Memory Interface Specifications
Table 1–26
specifications for the Stratix III device family.
00001111
10010000
10101010
01010101
max
.
through
Stratix III Device Datasheet: DC and Switching Characteristics
Conditions
Transition
Table 1–33
Density
100%
10%
25%
50%
—
list the external memory interface
Notes
Min
256
256
256
256
256
Stratix III Device Handbook, Volume 2
(1), (2),
Min
Typ
(5)
—
—
—
—
—
(7)
- Preliminary
Typ
-2 Speed Grade
—
Max
—
—
—
—
—
Max
—
Number of
repetitions
Number of
repetitions
Number of
repetitions
Number of
repetitions
Number of
repetitions
Unit
Unit
UI
1–21