EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 324

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Differential Transmitter
Figure 9–5. Receiver Block Diagram
Figure 9–6. Stratix III Deserializer Bypass
9–8
Stratix III Device Handbook, Volume 1
Up to 1.25 Gbps
Eight Phase Clocks
rx_inclk
rx_in
+
–
data retimed_data
PLL _Lx /
The Stratix III deserializer can be bypassed in the Quartus II MegaWizard
to support DDR(×2) or SDR(×1) operations. The DPA and the data
realignment circuit cannot be used when the deserializer is bypassed. The
IOE contains two data input registers that can operate in DDR or SDR
mode. The clock source for the registers in the IOE can come from any
routing resource, from the left/right PLLs or from the top/bottom PLLs.
Figure 9–6
PLL_Rx
DPA
8
DPA_clk
shows the deseralizer bypass data path.
Circuitry
diffioclk
load_en
DPA
Synchronizer
D
DPA Bypass Multiplexer
Q
IOE Supports SDR, DDR, or
Non-Registered Data Path
Deserializer
IOE
Realignment
Circuitry
Data
Dedicated
Receiver
Interface
PLD Logic
Array
Altera Corporation
Regional or
Global Clock
10
November 2007
Internal
Logic