EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 247

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 7–12. Dynamic Parallel OCT in Stratix III Devices
Altera Corporation
November 2007
Receiver
50 Ω
50
Transmitter
50 Ω
Stratix III OCT
Stratix III OCT
f
VCCIO
VCCIO
GND
GND
100 Ω
100 Ω
100 Ω
100
100 Ω
100
For more information about tolerance specifications for on-chip
termination with calibration, refer to the
of Stratix III Devices
LVDS Input On-Chip Termination (R
Stratix III devices support on-chip termination for differential LVDS input
buffers with a nominal resistance value of 100 Ω, as shown in
Figure
I/O banks; column I/O banks do not support OCT R
clock input pairs CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n,
CLK10p, and CLK10n on the row I/O banks of the Stratix III devices do
not support R
7–13. Differential on-chip termination R
D
termination.
chapter in volume 2 of the Stratix III Device Handbook.
Z
Z
O
O
= 50 Ω
= 50 Ω
100 Ω
100 Ω
100 Ω
100 Ω
Stratix III Device Handbook, Volume 1
100 Ω
100
100 Ω
100
D
VCCIO
DC and Switching Characteristics
)
VCCIO
GND
GND
Stratix III Device I/O Features
Stratix III OCT
Stratix III OCT
D
is only available in row
Transmitter
D.
The dedicated
Receiver
50 Ω
50 Ω
50
7–29