EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 530

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EP3SE50F780I3N

Manufacturer Part Number
EP3SE50F780I3N
Description
Stratix III
Manufacturer
Altera
Datasheets

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Switching Characteristics
1–18
Stratix III Device Handbook, Volume 2
M144K
Table 1–20. Stratix III TriMatrix Memory Block Performance Specifications (Part 2 of 2)
Block Type
Memory
Single-port
2K×72
Simple
dual-port
2K×72 dual
clock
Simple
dual-port
2K×64 dual
clock
(with ECC)
True dual-port
4K×36 dual
clock
Mode
Configuration and JTAG Specifications
Table 1–21
Note to
(1)
Passive Serial
Fast Passive Parallel
Fast Active Serial
Remote Update only in Fast AS mode
Table 1–21. Stratix III Configuration Mode Specifications - Preliminary
ALUTs
0
0
0
0
Data rate must be 4× slower than the clock when Decompression and/or
Encryption are used.
Table
TriMatrix
Memory
lists the Stratix III Configuration Mode Specifications.
Programming Mode
1
1
1
1
1–21:
V
C C L
(1)
-2 Speed
Grade
600
600
333
600
= 1.1V V
C C L
-3 Speed
Grade
500
500
275
500
= 1.1V
V
C C L
-4 Speed
Grade
DCLK F
450
450
250
450
= 1.1V
100
100
40
10
max
Altera Corporation
V
C C L
November 2007
450
450
250
450
= 1.1V V
-4L Speed
MHz
MHz
MHz
MHz
Unit
Grade
C C L
325
325
200
325
Preliminary
= 0.9V
MHz
MHz
MHz
MHz
Unit

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