EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 382

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Fast Active Serial Configuration (Serial Configuration Devices)
11–22
Stratix III Device Handbook, Volume 1
Serial configuration devices have a four-pin interface: serial clock input
(DCLK), serial data output (DATA), AS data input (ASDI), and an
active-low chip select (nCS). This four-pin interface connects to Stratix III
device pins, as shown in
Figure 11–8. Single Device Fast AS Configuration
Notes to
(1)
(2)
Upon power-up, the Stratix III devices go through a POR. The POR delay
is dependent on the PORSEL pin setting. When PORSEL is driven low, the
POR time is approximately 100 ms. If PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
nSTATUS and CONF_DONE low, and tri-state all user I/O pins. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
After POR, the Stratix III device releases nSTATUS, which is pulled high
by an external 10-kΩ pull-up resistor and enters configuration mode.
1
Serial Configuration
Connect the pull-up resistors to a 3.3-V supply.
Stratix III devices use the ASDO-to-ASDI path to control the configuration device.
Device
Figure
To begin configuration, power the V
V
pins reside) to the appropriate voltage levels.
CCPD
DATA
DCLK
ASDI
nCS
11–8:
voltages (for the banks where the configuration and JTAG
V
CC
10 kΩ
(1)
Figure
V
(2)
CC
10 kΩ
11–8.
(1)
GND
V
CC
10 kΩ
(1)
nCONFIG
nSTATUS
CONF_DONE
nCE
DATA0
DCLK
nCSO
ASDO
CC
Stratix III FPGA
, V
CCIO
, V
Altera Corporation
MSEL2
MSEL1
MSEL0
nCEO
CCPGM
November 2007
, and
V
CCPGM
N.C.
GND