EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 315

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Conclusion
Altera Corporation
November 2007
Programmable Drive Strength
You can choose the optimal drive strength needed for your interface after
performing a board simulation. Higher drive strength helps provide a
larger voltage swing, which in turn provides bigger eye diagrams with
greater timing margin. However, higher drive strengths typically require
more power, faster slew rates and add to simultaneous switching noise.
You can use the programmable slew rate control along with this feature
to minimize simultaneous switching noise with higher drive strengths.
This feature is also disabled if you are using the OCT R
the default drive strength in Stratix III devices. You should use the OCT
R
setting for bi-directional data signals. You need to simulate the system to
determine the drive strength needed for command, address, and clock
signals.
PLL
PLLs are used to generate the memory interface controller clocks, like
the 0° system clock, the –90° or 270° phase-shifted write clock,
the half-rate PHY clock, and the resynchronization clock. The PLL
reconfiguration feature can be used to calibrate the resynchronization
phase shift to balance the setup and hold margin.
The VCO and counter setting combinations may be limited for high
performance memory interfaces.
1
Stratix III devices have many features available to support existing and
emerging external memory interfaces. The ALTMEMPHY megafunction,
built to support the Stratix III memory interface features, allows
customers to easily implement their data path for use with either their
own controller or Altera’s IP controller.
In Stratix III devices, most of the critical data transfers are taken care of
for you in the IOE, alleviating the burden of having to close timing in the
FPGA fabric. Furthermore, since most of the registers are in the IOE, data
delays between registers are short, allowing the circuitry to work at a
higher frequency. Dynamically calibrated OCT, slew rate adjustment,
and programmable drive strength improve signal integrity, especially at
higher frequencies of operation.
T/
R
S
setting for uni-directional read/write data and dynamic OCT
For more information about the Stratix III PLL, refer to the
Clock Networks and PLLs in Stratix III Devices
of the Stratix III Device Handbook.
External Memory Interfaces in Stratix III Devices
Stratix III Device Handbook, Volume 1
chapter in volume 1
S
feature, which is
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