EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 126

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Operational Mode Descriptions
5–26
Stratix III Device Handbook, Volume 1
two multiplier outputs. Summation or subtraction has to be selected at
compile time. The Two-Multiplier Adder function is useful for
applications such as FFTs, complex FIR, and IIR filters.
the DSP block configured in the two-multiplier adder mode.
The loopback mode is the other sub-feature of the two-multiplier adder
mode.
mode. This mode takes the 36-bit summation result of the two multipliers
and feeds back the most significant 18-bits to the input. The lower 18-bits
are discarded. You have the option to disable or zero-out the loopback
data by using the dynamic zero_loopback signal. A logic 1 value on
the zero_loopback signal selects the zeroed data or disables the
looped back data, while a logic 0 selects the looped back data.
1
For the Two-Multiplier Adder mode, if all the inputs are full 18-bit and
unsigned, the result will require 37 bits. As the output data width in
Two-Multiplier Adder mode is limited to 36 bits, this 37-bit output
requirement is not allowed. Any other combination that does not violate
the 36-bit maximum result is permitted; for example, two 16 × 16 signed
Two-Multiplier Adders is valid.
The two-multiplier adder mode supports the round and saturation logic
unit. You can use the pipeline registers and output registers within the
DSP block to pipeline the multiplier-adder result, increasing the
performance of the DSP block.
Figure 5–15
The option to use the loopback mode or the general
two-multiplier adder mode must be selected at compile time.
shows the DSP block configured in the loopback
Figure 5–14
Altera Corporation
October 2007
shows