EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 878

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–366
Stratix III Device Handbook, Volume 2
RCLK output adder
RCLK PLL output adder
tcin
tcout
tpllcin
tpllcout
Parameter
Table 1–144. EP3SE260 Row Pin Delay Adders for Regional Clock (Part 2 of 2)
Table 1–146. EP3SL50 Column Pin Global Clock Timing Specifications
Parameter
Industrial Commercial V
—
—
—
—
Fast Model
Industrial
1.542
1.542
0.371
0.371
Dedicated Clock Pin Timing
Table 1–145
when the clock is driven by global clock, regional clock, periphery clock
and a PLL.
Table 1–145
EP3SL50 Clock Timing Parameters
Table 1–146
EP3SL50 devices.
—
—
t
t
t
t
C I N
C O U T
P L L C I N
P L L C O U T
Table 1–145. Stratix III Clock Timing Parameters
Fast Model
Symbol
Commercial
CCL
0.014
0.08
and
to
describes Stratix III clock timing parameters.
2.403
2.403
0.541
0.541
-2
=1.1V V
Table 1–205
Delay from clock pad to I/O input register
Delay from clock pad to I/O output register
Delay from PLL
Delay from PLL
Table 1–147
V
CCL
2.695
2.695
0.629
0.629
CCL
-3
=1.1V V
—
—
-2
=1.1V
show clock pin timing for Stratix III devices
show the global clock timing parameters for
inclk
inclk
CCL
V
2.912
2.912
0.630
0.630
CCL
-4
=1.1V V
0.151
0.064
pad to I/O input register
pad to I/O output register
-3
=1.1V
Parameter
CCL
2.777
2.777
0.599
0.599
V
CCL
=1.1V V
0.392
0.268
-4
=1.1V
-4L
Altera Corporation
CCL
3.244
3.244
0.902
0.902
November 2007
V
=0.9V
CCL
0.322
0.103
-4L
=1.1V
Units
ns
ns
ns
ns
Units
ns
ns