EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 478

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

User Mode Error Detection
15–4
Stratix III Device Handbook, Volume 1
f
The error detection circuitry in Stratix III devices uses a 16-bit CRC-ANSI
standard (16-bit polynomial) as the CRC generator.
The computed 16-bit CRC signature for each frame is stored in the
registers within the core. The total storage register size is 16 (number of
bits per frame) × the number of frames.
The Stratix III device error detection feature does not check memory
blocks and I/O buffers. These memory blocks support parity bits that are
used to check the contents of memory blocks for any error. The I/O
buffers are not verified during error detection because these bits use
flip-flops as storage elements that are more resistant to soft errors
compared to CRAM cells.
The M144K TriMatrix memory block has a built-in error correction code
block that checks and corrects the errors in the block. However, for logic
array blocks (LABs) that are used as MLAB memory blocks, they are
ignored during error detection verification. Thus, the CRC_ERROR signal
may stay solid high or low depending on the error status of the previous
checked CRAM frame.
For more information on error detection in the Stratix III TriMatrix
memory blocks, refer to the
Stratix III Devices
In order to provide testing capability of the error detection block, a JTAG
instruction EDERROR_INJECT is provided. This instruction is able to
change the content of the 21-bit JTAG fault injection register, used for
error injection in Stratix III devices, hence enabling the testing of the error
detection block.
1
Table 15–1
instruction.
EDERROR_INJECT
Table 15–1. EDERROR_INJECT JTAG Instruction
JTAG Instruction
You can only execute the EDERROR_INJECT JTAG instruction
when the device is in user mode.
shows the description of the EDERROR_INJECT JTAG
chapter in volume 1 of the Stratix III Device Handbook.
Instruction Code
00 0001 0101
TriMatrix Embedded Memory Blocks in
This instruction controls the 21-bit
JTAG fault injection register, which is
used for error injection.
Description
Altera Corporation
October 2007