EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 166

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clock Networks in Stratix III Devices
6–16
Stratix III Device Handbook, Volume 1
Figure 6–10. Clock Input Multiplexer Logic for L1, L4, R1, and R4 PLLs
Notes to
(1)
(2)
(3)
Clock Control Block
Every global and regional clock network has its own clock control block.
The control block provides the following features:
■
■
■
Figures 6–11
blocks, respectively.
You can select the clock source for the global clock select block either
statically or dynamically. You can either statically select the clock source
using a setting in the Quartus II software, or you can dynamically select
the clock source using internal logic to drive the multiplexer select inputs.
When selecting the clock source dynamically, you can either select two
PLL outputs (such as CLK0 or CLK1), or a combination of clock pins or
PLL outputs.
Dedicated clock input pins to PLLs - L1, L4, R1 and R4, respectively. For example,
PLL_L1_CLK is the dedicated clock input for PLL_L1.
The global (GCLK) or regional (RCLK) clock input can be driven by an output from
another PLL, a pin-driven global or regional clock, or through a clock control block
provided the clock control block is fed by an output from another PLL or a pin
driven dedicated global or regional clock. An internally generated global signal or
general purpose I/O pin cannot drive the PLL.
The center clock pins can feed the corner PLLs on the same side directly, through
a dedicated path. However, these paths may not be fully compensated.
Clock source selection (dynamic selection for global clocks)
Global clock multiplexing
Clock power down (static or dynamic clock enable or disable)
Figure
PLL_<L1/L4/R1/R4>_CLK (1)
CLK[0..3] or CLK[8..11] (3)
and
6–10:
6–12
GCLK/RCLK (2)
show the global clock and regional clock select
4
4
Altera Corporation
November 2007
inclk0
inclk1