EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 311

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
There are three registers in the DDR input registers block. Two registers
capture data on the positive and negative edges of the clock, while the
third register aligns the captured data. You can choose to have the same
clock for the positive edge and negative edge registers, or two different
clocks (DQS for positive edge register, and CQn for negative edge
register). The third register that aligns the captured data uses the same
clock as the positive edge registers.
The resynchronization registers consist of up to three levels of registers to
resynchronize the data to the system clock domain. These registers are
clocked by the resynchronization clock that is either generated by the PLL
or the read-leveling delay chain. The outputs of the resynchronization
registers can go straight to the core or to the HDR blocks, which are
clocked by the divided-down resynchronization clock.
For more information about the read-leveling delay chain, refer to the
“Leveling Circuitry” on page
Figure 8–21
output-enable paths. The path is divided into the HDR block,
resynchronization registers, and output/output-enable registers. The
device can bypass each block of the output and output-enable path.
shows the registers available in the Stratix III output and
External Memory Interfaces in Stratix III Devices
8–36.
Stratix III Device Handbook, Volume 1
8–41