EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 326

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Differential Transmitter
Figure 9–8. DPA Clock Phase to Serial Data Timing Relationship
9–10
Stratix III Device Handbook, Volume 1
rx_in
135˚
180˚
225˚
270˚
315˚
45˚
90˚
0˚
0.125T
D0
Dynamic Phase Aligner (DPA)
The DPA block takes in high-speed serial data from the differential input
buffer and selects one of the eight phase clocks from the left/right PLL to
sample the data. The DPA chooses a phase closest to the phase of the
serial data. The maximum phase offset between the received data and the
selected phase is 1/8UI, which is the maximum quantization error of the
DPA. The eight phases of the clock are equally divided, giving a
45
between the DPA clocks and the incoming serial data.
The DPA block continuously monitors the phase of the incoming serial
data and selects a new clock phase if needed. You can prevent the DPA
from selecting a new clock phase by asserting the optional
RX_DPLL_HOLD port, which is available for each channel.
The DPA block requires a training pattern and a training sequence of at
least 256 repetitions. The training pattern is not fixed, so you can use any
training pattern with at least one transition on each channel. An optional
output port, RX_DPA_LOCKED, is available to the internal logic to indicate
when the DPA block has settled on the closest phase to the incoming data
phase. The DPA block deasserts RX_DPA_LOCKED depending on the
option selected in the Quartus II MegaWizard Plug-In Manager, when
either a new phase is selected, or when the DPA has moved two phases
in the same direction. The RX_DPA_LOCKED signal is synchronized to the
DPA clock domain and should be considered as the initial indicator for
the lock condition. Use data checkers to validate the data integrity.
vco
o
resolution.
D1
Figure 9–8
T
D2
vco
shows the possible phase relationships
D3
D4
Dn
Altera Corporation
November 2007