EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 405

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 11–19. JTAG Configuration of a Single Device Using a Download Cable
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
November 2007
You should connect the pull-up resistor to the same supply voltage as the USB Blaster, MasterBlaster (V
ByteBlaster II, or ByteBlasterMV cable. The voltage supply can be connected to the V
You should connect the nCONFIG and MSEL[2..0] pins to support a non-JTAG configuration scheme. If you only
use the JTAG configuration, connect nCONFIG to V
whichever is convenient on your board.
Pin 6 of the header is a V
V
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
You must connect nCE to GND or driven low for successful JTAG configuration.
CCIO
Figure
. Refer to the
V
CC
11–19:
(1)
10 kΩ
V
CC
MasterBlaster Serial/USB Communications Cable Data Sheet
GND
(1)
10 kΩ
(2)
(2)
(2)
IO
N.C.
reference voltage for the MasterBlaster output driver. V
To configure a single device in a JTAG chain, the programming software
places all other devices in bypass mode. In bypass mode, devices pass
programming data from the TDI pin to the TDO pin through a single
bypass register without being affected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon
completion. At the end of configuration, the software checks the state of
CONF_DONE through the JTAG port. When Quartus II generates a JAM
file (.jam) for a multi-device chain, it contains instructions so that all the
devices in the chain will be initialized at the same time. If CONF_DONE is
not high, the Quartus II software indicates that configuration has failed.
nCE0
nCE (4)
nSTATUS
CONF_DONE
nCONFIG
MSEL[2..0]
DCLK
Stratix III Device
TRST
TDO
TMS
TCK
TDI
CC
, and MSEL[2..0] to ground. Pull DCLK either high or low,
10 kΩ
V
CC
V
CC
(1)
V
CC
10 kΩ
(1)
1 kΩ
Stratix III Device Handbook, Volume 1
GND
Pin 1
for this value. In the ByteBlasterMV
10-Pin Male Header
Configuring Stratix III Devices
Download Cable
(JTAG Mode)
(Top View)
IO
GND
CCPD
should match the device's
V
V
of the device.
CC
IO
(3)
GND
IO
pin),
11–45