EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 269

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Document
Revision History
Altera Corporation
November 2007
November 2007
v1.3
October 2007
v1.2
May 2007
v1.1
November 2006
v1.0
Table 7–9. Document Revision History
Date and Document
Version
●
●
●
●
●
●
●
●
●
●
●
●
●
Added the feature programmable input delay to “Stratix III I/O
Structure” on page 7–13. Updated Table 7–4 and Table 7–7.
Updated “LVDS Input On-Chip Termination (RD)” on page 7–29.
Updated Figure 7–3 through Figure 7–7. Updated Figure 7–23,
Figure 7–24. Minor text edits to page 14.
Initial Release
Updated
and
Updated
Minor text edits to second to last paragraph on pg 7-47.
Updated Table 7–2, Table 7–4, Table 7–5, Table 7–8.
Updated “Introduction”, “OCT Calibration Block Modes of
Operation”, “Power Up Mode”, “User Mode”.
Changed 3.0-V LVTTL and 3.0-V LVCMOS to be 3.3/3.0-V
LVTTL and 3.3/3.0-V LVCMOS throughout the document.
Added a note to Figure 7–1, Figure 7–3, Figure 7–4,
Figure 7–5, Figure 7–6, Figure 7–7, Figure 7–14,
Figure 7–15, Figure 7–16, and Figure 7–17.
Updated Figure 7–8, Figure 7–18, Figure 7–22, Figure 7–23,
Figure 7–25, Figure 7–28, and Figure 7–29.
Added Figure 7–18 and Figure 7–20.
Expanded “3.3-V I/O Interface” on page 7–15 to include new
information.
Removed section “OCT Calibration Block Architecture”,
“OCT Calibration Block Ports”, and “OCT Calibration Block
Code Data Transfer”.
Added section “OCT Calibration”, “Serial Data Transfer”,
“Example of Using Multiple OCT Calibration Blocks”, “RS
Calibration”, and “Referenced Documents.”
Added live links for references.
Table 7–9
Figure
Figure
Note (1)
7–16.
shows the revision history for this document.
7–4,
of
Figure
Changes Made
Figure
7–25.
7–5,
Figure
7–6,
Stratix III Device Handbook, Volume 1
Figure
7–15,
Stratix III Device I/O Features
Text changes, figure
updates, removal of
Figure updates.
Summary of
a section.
Changes
—
—
7–51