EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 183

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Figure 6–21. Phase Relationship Between Clock and Data in Source-
Synchronous and LVDS Modes
The source-synchronous mode compensates for the delay of the clock
network used plus any difference in the delay between these two paths:
■
■
1
Source-Synchronous Mode for LVDS Compensation
The goal of this mode is to maintain the same data and clock timing
relationship seen at the pins at the internal SERDES capture register,
except that the clock is inverted (180-degree phase shift). Thus, this mode
ideally compensates for the delay of the LVDS clock network plus any
difference in delay between these two paths:
■
■
Data pin to IOE register input
Clock input pin to the PLL PFD input
Data pin-to-SERDES capture register
Clock input pin-to-SERDES capture register. In addition, the output
counter needs to provide the 180-degree phase shift.
Set the input pin to register delay chain within the IOE to zero
in the Quartus II software for all data pins clocked by a
source-synchronous mode PLL. Also, all data pins need to use
the PLL COMPENSATED logic option in the Quartus II
software.
Clock at register
reference clock
Data at register
at input pin
Data pin
PLL
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
6–33