EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 330

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Left/Right PLLs (PLL_Lx/ PLL_Rx)
Left/Right PLLs
(PLL_Lx/
PLL_Rx)
Figure 9–12. PLL Block Diagram
Notes to
(1)
(2)
(3)
(4)
9–14
Stratix III Device Handbook, Volume 1
from adjacent PLL
n = 6 for Left/Right PLLs; n = 9 for Top/Bottom PLLs.
This is the VCO post-scale counter
The FBOUT port is fed by the M counter in Stratix III PLLs.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal or general purpose
I/O pin cannot drive the PLL.
Cascade input
GCLK/RCLK
Clock inputs
pfdena
from pins
Figure
(4)
9–12:
f
4
inclk0
inclk1
Switchover
Stratix III devices contain up to eight left/right PLLs with up to four PLLs
located on the left side and four on the right side of the device. The left
PLLs can support high-speed differential I/O banks on the left side and
the right PLLs can support banks on the right side of the device. The
high-speed differential I/O receiver and transmitter channels use these
left/right PLLs to generate the parallel global clocks (rx- or tx-clock) and
high-speed clocks (diffioclk).
left/right PLLs. The PLL VCO operates at the clock frequency of the data
rate. Each left/right PLL offers a single serial data rate support, but up to
two separate serialization and/or deserialization factors (from the C0 and
C1 left/right PLL clock outputs). Clock switchover and dynamic
left/right PLL reconfiguration is available in high-speed differential I/O
support mode.
For more details, refer to the
chapter in volume 1 of the Stratix III Device Handbook.
Figure 9–12
of the Stratix III PLL.
Clock
Block
K
÷n
clkswitch
clkbad0
clkbad1
activeclock
.
shows a simplified block diagram of the major components
PFD
Circuit
Lock
CP
locked
LF
Clock Network and PLLs in Stratix III Devices
VCO
Figure 9–1
8
no compensation mode
ZDB, External feedback modes
LVDS Compensation mode
Source Synchronous, normal modes
÷2
(2)
To DPA block on
Left/Right PLLs
/2, /4
8
shows the locations of the
8
÷C0
÷C1
÷C2
÷C3
÷Cn
÷m
(1)
Altera Corporation
November 2007
Casade output
to adjacent PLL
FBIN
DIFFIOCLK network
GCLK/RCLK network
GCLKs
RCLKs
DIFFIOCLK from
Left/Right PLLs
LOAD_EN from
Left/Right PLLs
FBOUT (3)
External
memory
interface DLL
External clock
outputs