EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 158

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clock Networks in Stratix III Devices
6–8
Stratix III Device Handbook, Volume 1
Figure 6–8. Twelve Independent Sub-Regional + One Regional Clock Region
Clock Network Sources
In Stratix III devices, clock input pins, PLL outputs, and internal logic can
drive the global and regional clock networks. See
connectivity between dedicated CLK[0..15] pins and the global and
regional clock networks.
Dedicated Clock Inputs Pins
The CLK pins can either be differential clocks or single-ended clocks.
Stratix III devices supports 16 differential clock inputs or 32 single-ended
clock inputs. You can also use the dedicated clock input pins
CLK[15..0] for high fan-out control signals such as asynchronous
clears, presets, and clock enables for protocol signals such as TRDY and
IRDY for PCI through global or regional clock networks.
Logic Array Blocks (LABs)
You can also drive each global and regional clock network via
LAB-routing to enable internal logic to drive a high fan-out, low-skew
signal.
1
PLL Clock Outputs
Stratix III PLLs can drive both GCLK and RCLK networks, as shown in
Tables 6–8
Stratix III device PLLs cannot be driven by internally generated
GCLKs or RCLKs. The input clock to the PLL has to come from
dedicated clock input pins or pin/PLL-fed GCLKs or RCLKs
only.
and 6–9.
Tables 6–2
Altera Corporation
November 2007
to
6–6
for the