EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 613

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EP3SE50F780I3N

Manufacturer Part Number
EP3SE50F780I3N
Description
Stratix III
Manufacturer
Altera
Datasheets

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Altera Corporation
November 2007
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
3.0-V LVTTL
3.0-V LVTTL
3.0-V LVTTL
3.0-V
LVCMOS
3.0-V
LVCMOS
I/O Standard
Table 1–58. EP3SL70 Row Pins Output Timing Parameters (Part 1 of 5)
Strength
Current
12mA
12mA
4mA
8mA
4mA
8mA
4mA
8mA
4mA
8mA
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Table 1–58
single-ended I/O standards.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
specifies EP3SL70 Row Pins Output Timing parameters for
Stratix III Device Datasheet: DC and Switching Characteristics
Industrial Commercial
Fast Model
3.620
2.486
3.452
2.318
3.700
2.566
3.619
2.485
3.605
2.471
3.620
2.486
3.452
2.318
3.700
2.566
3.619
2.485
3.605
2.471
Stratix III Device Handbook, Volume 2
5.343 5.985 6.264 6.110 6.285
3.513 3.928 3.986 3.963 3.943
5.099 5.709 5.988 5.834 6.009
3.269 3.652 3.710 3.687 3.667
5.465 6.131 6.410 6.256 6.431
3.635 4.074 4.132 4.109 4.089
5.353 6.000 6.279 6.125 6.300
3.523 3.943 4.001 3.978 3.958
5.309 5.954 6.233 6.079 6.254
3.479 3.897 3.955 3.932 3.912
5.343 5.985 6.264 6.110 6.285
3.513 3.928 3.986 3.963 3.943
5.099 5.709 5.988 5.834 6.009
3.269 3.652 3.710 3.687 3.667
5.465 6.131 6.410 6.256 6.431
3.635 4.074 4.132 4.109 4.089
5.353 6.000 6.279 6.125 6.300
3.523 3.943 4.001 3.978 3.958
5.309 5.954 6.233 6.079 6.254
3.479 3.897 3.955 3.932 3.912
V
1.1V
CCL
-2
=
V
1.1V
CCL
-3
=
V
1.1V
CCL
-4
=
V
1.1V
CCL
=
1–101
-4L
V
0.9V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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