EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 285

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 8–7. DQS/DQ Bus Mode Support per Bank in EP3SL340 Devices in 1760-pin FineLine
BGA Package
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
November 2007
I/O Bank 1C (4)
50 User I/Os (3)
50 User I/Os (3)
50 User I/Os (3)
50 User I/Os (3)
I/O Bank 1A (2)
I/O Bank 2A (2)
Numbers are preliminary.
Some of the ×4 groups may use R
these pins as R
All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n,
CLK10p, and CLK10n) and eight dedicated corner PLL clock inputs (PLL_L1_CLKp, PLL_L1_CLKn,
PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, and PLL_R1_CLKn) that can
be used for data inputs.
Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are
not going to be used by your configuration scheme.
36 User I/Os
36 User I/Os
I/O Bank 1B
I/O Bank 2C
I/O Bank 2B
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
DLL1
x4=7
x4=6
x4=7
x4=7
x4=6
x4=7
DLL2
Figure
Note (1)
8–7:
I/O Bank 8A (2)
I/O Bank 3A (2)
48 User I/Os
48 User I/Os
UP
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
and R
DN
pins for OCT calibration.
I/O Bank 8B
I/O Bank 3B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x81x9=4
x8/x9=4
x4=8
x4=8
UP
/R
DN
pins as DQ pins. You lose one DQS/DQ group (in any mode) if you use
I/O Bank 3C (2)
I/O Bank 8C (2)
48 User I/Os
48 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
x4=6
x4=6
1760-pin FineLine BGA
EP3SL340 Devices
48 User I/Os
48 User I/Os
I/O Bank 4C
I/O Bank 7C
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
External Memory Interfaces in Stratix III Devices
x4=6
x4=6
Stratix III Device Handbook, Volume 1
48 User I/Os
48 User I/Os
I/O Bank 7B
I/O Bank 4B
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
I/O Bank 7A (2)
I/O Bank 4A (2)
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
I/O Bank 6A (2)
I/O Bank 5A (2)
50 User I/Os (3)
50 User I/Os (3)
50 User I/Os (3)
36 User I/Os (3)
50 User I/Os (3)
I/O Bank 6B
I/O Bank 6C
I/O Bank 5C
I/O Bank 5B
36 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
DLL3
x4=7
x4=6
x4=7
x4=7
x4=6
x4=7
DLL4
8–15