EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 303

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
DQS Delay Chain
The DQS delay chains consist of a set of variable delay elements to allow
the input DQS and CQn signals to be shifted by the amount specified by
the DQS phase-shift circuitry or the logic array. There are four delay
elements in the DQS delay chain; the first delay chain closest to the DQS
pin can either be shifted by the DQS delay settings or by the sum of the
DQS delay setting and the phase-offset setting. The number of delay
chains required is transparent to the users because the ALTMEMPHY
megafunction automatically sets it when you choose the operating
frequency. The DQS delay settings can come from the DQS phase-shift
circuitry on either end of the I/O banks or from the logic array.
The delay elements in the DQS logic block have the same characteristics
as the delay elements in the DLL. When the DLL is not used to control the
DQS delay chains, you can input your own Gray-coded 6-bit or 5-bit
settings using the dqs_delayctrlin[5..0]signals available in the
ALTMEMPHY megafunction. These settings control 1, 2, 3, or all 4 delay
elements in the DQS delay chains. The ALTMEMPHY megafunction can
also dynamically choose the number of DQS delay chains needed for the
system. The amount of delay is equal to the sum of the delay element’s
intrinsic delay and the product of the number of delay steps and the value
of the delay steps.
You can also bypass the DQS delay chain to achieve 0° phase shift.
Update Enable Circuitry
Both the DQS delay settings and the phase-offset settings pass through a
register before going into the DQS delay chains. The registers are
controlled by the update enable circuitry to allow enough time for any
changes in the DQS delay setting bits to arrive at all the delay elements.
This allows them to be adjusted at the same time. The update enable
circuitry enables the registers to allow enough time for the DQS delay
settings to travel from the DQS phase-shift circuitry or core logic to all the
DQS logic blocks before the next change. It uses the input reference clock
or a user clock from the core to generate the update enable output. The
ALTMEMPHY megafunction uses this circuit by default. See
for an example waveform of the update enable circuitry output.
External Memory Interfaces in Stratix III Devices
Stratix III Device Handbook, Volume 1
Figure 8–14
8–33