EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 28

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Architecture Features
1–10
Stratix III Device Handbook, Volume 1
f
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A self-calibrating soft IP core (ALTMEMPHY) optimized to take
advantage of Stratix III device I/O along with the new Quartus II timing
analysis tool (TimeQuest) provide the total solution for the highest
reliable frequency of operation across process voltage and temperature.
For more information on external memory interfaces, refer to the
External Memory Interfaces in Stratix III Devices
Stratix III Device Handbook.
High Speed Differential I/O Interfaces with DPA
Stratix III devices contain dedicated circuitry for supporting differential
standards at speeds up to 1.25 Gbps. The high-speed differential I/O
circuitry supports the following high speed I/O interconnect standards
and applications: Utopia IV, SPI-4.2, SFI-4, 10 Gigabit Ethernet XSLI,
Rapid I/O, and NPSI. Stratix III devices support 2×, 4×, 6×, 7×, 8× and 10×
SERDES modes for high speed differential I/O interfaces and 4×, 6×, 7×,
8× and 10× SERDES modes when using the dedicated DPA circuitry.
DPA minimizes bit errors, simplifies PCB layout and timing management
for high-speed data transfer, and eliminates channel-to-channel and
channel-to-clock skew in high-speed data transmission systems. Soft
CDR can also be implemented, enabling low-cost 1.25-Gbps clock
embedded serial links.
Stratix III devices have the following dedicated circuitry for high-speed
differential I/O support:
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For more information, refer to the
with DPA in Stratix III Devices
Handbook.
Hot Socketing and Power-On Reset
Stratix III devices are hot-socketing compliant. Hot socketing is also
known as hot plug-in or hot swap, and power sequencing support
without the use of any external devices. Robust on-chip hot-socketing
and power-sequencing support ensures proper device operation
independent of the power-up sequence. You can insert or remove a
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
Dynamic phase aligner (DPA)
Soft CDR functionality
Synchronizer (FIFO buffer)
PLLs
chapter in volume 1 of the Stratix III Device
High Speed Differential I/O Interfaces
chapter in volume 1 of the
Altera Corporation
November 2007