EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 722

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–210
Stratix III Device Handbook, Volume 2
DIFFERENTIAL
1.8-V SSTL
CLASS I
DIFFERENTIAL
1.8-V SSTL
CLASS II
DIFFERENTIAL
1.8-V SSTL
CLASS II
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
RCLK input
adder
RCLK PLL
input adder
Table 1–92. EP3SL200 Row Pins Output Timing Parameters (Part 4 of 4)
Table 1–93. EP3SL200 Column Pin Delay Adders for Regional Clock (Part 1 of 2)
Parameter
I/O Standard
Industrial Commercial V
Strength
Current
12mA
16mA
12mA
16mA
—
—
8mA
8mA
Fast Model
Table 1–93
values that should be added to GCLK values. These adder values are
used to determine I/O timing when I/O pin is driven using regional
clock. This applies for all I/O standards supported by Stratix III devices.
Table 1–93
Regional Clock.
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
1.956
1.888
Parameter
and
specifies EP3SL200 Column Pin delay adders when using the
t
t
t
t
t
t
t
t
t
t
t
t
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CCL
2.983
2.871
Table 1–94
-2
=1.1V V
Industrial Commercial
—
—
—
—
—
—
—
—
—
—
—
—
CCL
3.293
3.158
show EP3SL200 regional clock (RCLK) adder
Fast Model
-3
=1.1V V
3.102
1.442
3.096
1.437
3.099
1.438
3.103
1.446
3.100
1.442
3.098
1.438
CCL
3.632
3.47
-4
=1.1V V
V
4.975 5.554 5.897 5.722 6.061
2.374 2.678 2.749 2.712 2.698
4.965 5.543 5.885 5.711 6.050
2.364 2.667 2.737 2.701 2.687
4.967 5.545 5.888 5.713 6.052
2.366 2.669 2.740 2.703 2.689
4.982 5.563 5.906 5.731 6.070
2.381 2.687 2.758 2.721 2.707
4.974 5.553 5.896 5.721 6.060
2.373 2.677 2.748 2.711 2.697
4.967 5.545 5.888 5.713 6.052
2.366 2.669 2.740 2.703 2.689
1.1V
CCL
-2
CCL
=
3.46
3.31
=1.1V V
V
1.1V
CCL
-3
Altera Corporation
-4L
=
November 2007
V
1.1V
CCL
CCL
3.421
3.272
-4
=0.9V
=
V
1.1V
CCL
=
-4L
Units
ns
ns
V
0.9V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns