EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 541

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
t
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t
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Figure 1–2
Figure 1–2. Input Register Setup and Hold Timing Diagram
For output timing, different I/O standards require different baseline
loading techniques for reporting timing delays. Altera characterizes
timing delays with the required termination for each I/O standard and
with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the
timing is specified up to the output pin of the FPGA device. The Quartus
II software calculates the I/O timing for each I/O standard with a default
baseline loading as specified by the I/O standards.
The following measurements are made during device characterization.
Altera measures clock-to-output delays (t
minimum voltage, and maximum temperature (PVT) for default loading
conditions shown in
pin to output pin timing for Stratix III devices.
The t
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SU
H
=
=
+ data delay from input pin to input register
+ micro setup time of the input register
- clock delay from input pin to input register
- data delay from input pin to input register
+ micro hold time of the input register
+ clock delay from input pin to input register
+ delay from clock pad to I/O output register
+ IOE output register clock-to-output delay
+ delay from output register to output pin
CO
from clock pin to I/O pin =
shows the setup and hold timing diagram for input registers.
Stratix III Device Datasheet: DC and Switching Characteristics
Table
Input Clock Delay
Input Data Delay
1–35. The following equation describes clock
Stratix III Device Handbook, Volume 2
CO
) at worst-case process,
micro t
micro t
SU
H
1–29