EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 76

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Overview
4–2
Stratix III Device Handbook, Volume 1
Packed mode
Address clock enable
Single-port memory
Simple dual-port memory
True dual-port memory
Embedded shift register
ROM
FIFO buffer
Simple dual-port mixed
width support
True dual-port mixed
width support
Memory initialization file
(.mif)
Mixed-clock mode
Power-up condition
Register clears
Write/Read operation
triggering
Same-port
read-during-write
Mixed-port
read-during-write
ECC Support
Table 4–1. Summary of TriMatrix Memory Features (Part 2 of 2)
Feature
Outputs cleared
if registered,
otherwise reads
memory
contents.
Output registers
Write: Falling
clock edges
Read: Rising
clock edges
Outputs set to
old data or don’t
care
Outputs set to
don’t care
Soft IP support
via Quartus II
MLABs
v
v
v
v
v
v
v
v
—
—
—
—
Outputs cleared
Output registers
Write and Read:
Rising clock
edges
Outputs set to old
or new data
Outputs set to old
data
Soft IP support
via Quartus II
M9K Blocks
v
v
v
v
v
v
v
v
v
v
v
v
Altera Corporation
November 2007
Outputs cleared
Output registers
Write and Read:
Rising clock
edges
Outputs set to old
or new data
Outputs set to old
data
Built-in support in
×64 wide SDP
mode or soft IP
support via
Quartus II
M144K Blocks
v
v
v
v
v
v
v
v
v
v
v
v