EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 416

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Device Configuration Pins
11–56
Stratix III Device Handbook, Volume 1
nCE
nCEO
ASDO
nCSO
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 5 of 6)
Pin Name
mode, I/O in
mode, I/O in
User Mode
N/A in AS
N/A in AS
non-AS
non-AS
mode
mode
N/A
N/A
Configuration
Scheme
AS
AS
All
All
Pin Type
Output
Output
Output
Input
Active-low chip enable. The
the device with a low signal to allow
configuration. The
during configuration, initialization, and user
mode. In single device configuration, it should
be tied low. In multi-device configuration,
of the first device is tied low while its
is connected to
chain.
The
successful JTAG programming of the device.
Output that drives low when device
configuration is complete. In single device
configuration, this pin is left floating. In
multi-device configuration, this pin feeds the
next device's
device in the chain is left floating.
The
Control signal from the Stratix III device to the
serial configuration device in AS mode used to
read out configuration data.
In AS mode,
resistor that is always active.
Output control signal from the Stratix III device
to the serial configuration device in AS mode
that enables the configuration device.
In AS mode,
resistor that is always active.
nCE
nCEO
pin must also be held low for
pin is powered by V
ASDO
nCSO
nCE
nCE
Description
pin. The
nCE
has an internal pull-up
has an internal pull-up
of the next device in the
pin must be held low
Altera Corporation
nCEO
nCE
November 2007
CCPGM
pin activates
of the last
nCEO
.
nCE
pin