EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 307

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 8–18. Stratix III Read and Write Leveling Delay Chains and Multiplexers
Note to
(1)
Altera Corporation
November 2007
There is only one leveling delay chain per I/O bank with the same I/O number (for example I/O banks 1A, 1B,
and 1C). You can only have one memory controller in these I/O banks when the leveling delay chains are used.
Figure
Resynchronization
Leveling Circuitry and Multiplexers
Write clk
8–18:
(-90
DQS
clock
0
)
Because the data and read strobe signals are still point-to-point, special
consideration needs to be taken to ensure that the timing relationship
between CK/CK# and DQS signals (t
device on the modules. Furthermore, read data coming back into the
FPGA from the memory will also be staggered in a similar way. Stratix III
FPGAs have leveling circuitry to take care of these two needs. There is
one group of leveling circuitry per I/O bank, with the same I/O number
(for example, there is one leveling circuitry shared between I/O bank 1A,
1B, and 1C) located in the middle of the I/O bank. These delay chains are
PVT-compensated by the same DQS delay settings as the DLL and DQS
delay chains. For frequencies equal to and above 400 MHz, the DLL uses
eight delay chains such that each delay chain generates a 45
generated clock phases are distributed to every DQS logic block that is
available in the I/O bank. The delay chain taps, then feeds a multiplexer
controlled by the ALTMEMPHY megafunction to select which clock
phases are to be used for that ×4 or ×8 DQS group. Each group can use a
different tap output from the read-leveling/write-leveling delay chains
to compensate for the different CK/CK# delay going into each device on
the module.
circuitry.
The –90° write clock of the ALTMEMPHY megafunction feeds the
write-leveling circuitry to produce the clock to generate the DQS and DQ
signals. During initialization, the ALTMEMPHY megafunction picks the
correct write-leveled clock for the DQS and DQ clocks for each DQS/DQ
Read-Leveled Resynchronization Clock
Figure 8–18
Write-Leveled DQ Clock
Write-Leveled DQS Clock
illustrates the Stratix III read and write leveling
External Memory Interfaces in Stratix III Devices
I/O Clock
Divider
Stratix III Device Handbook, Volume 1
DQSS
Half-Rate Resynchronization Clock
) during a write is met at every
Note (1)
Half-Rate Source
Synchronous Clock
o
delay. The
8–37