EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 259

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 7–24. Stratix III Differential HSTL I/O Standard Termination
Altera Corporation
November 2007
Termination
External
On-Board
Termination
OCT
Differential HSTL Class I
Series OCT
Transmitter
Transmitter
50 Ω
Differential HSTL Class I
50 Ω
50 Ω
Z
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing,
low-power, general-purpose I/O interface standard. In Stratix III devices,
the LVDS I/O standard requires a 2.5-V V
buffer requires 2.5-V V
high-bandwidth data transfer, backplane drivers, and clock distribution.
LVDS requires a 100-Ω termination resistor between the two signals at
the input buffer. Stratix III devices provide an optional 100-Ω differential
termination resistor in the device using on-chip differential termination.
Figure 7–25
differential resistor is only available in row I/O banks. The one-resistor
topology is for a data rate of up to 200 Mbps. The three-resistor topology
is for data rates of higher than 200 Mbps.
Z
50 Ω
0
0
= 50 Ω
= 50 Ω
V TT V TT
V CCIO
50 Ω
GND
100 Ω
100 Ω
100 Ω
100 Ω
shows the details of LVDS termination. The on-chip
V CCIO
Receiver
Receiver
GND
CCPD
Differential HSTL Class II
Series OCT
. Use this standard in applications requiring
Transmitter
Transmitter
25 Ω
Stratix III Device Handbook, Volume 1
Differential HSTL Class II
50 Ω
V TT
V TT
V TT V TT
50 Ω
50 Ω
CCIO
Z
Z
0
0
= 50 Ω
= 50 Ω
Stratix III Device I/O Features
50 Ω
level. The LVDS input
50 Ω
50 Ω
50 Ω
V CCIO
V TT V TT
100 Ω
GND
100 Ω
100 Ω
100 Ω
50 Ω
V CCIO
Receiver
GND
Receiver
7–41