EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 82

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Overview
Figure 4–5. Output Latch Asynchronous Clear Waveform
4–8
Stratix III Device Handbook, Volume 1
aclr at latch
outclk
aclr
q
f
You can selectively enable asynchronous clears per logical memory via
the Quartus II RAM MegaWizard.
For more information, refer to the
Error Correction Code (ECC) Support
Stratix III M144K blocks have built-in support for error correction code
(ECC) when in
detect and correct data errors in the memory array. The M144K blocks
have a single-error-correction double-error-detection (SECDED)
implementation. SECDED can detect and fix a single bit error in a 64-bit
word or detect two bit errors in a 64-bit word. It cannot detect three or
more errors.
The M144K ECC status is communicated via a three-bit status flag
eccstatus[2..0]. The status flag can be either registered or
unregistered. When registered, it uses the same clock and asynchronous
clear signals as the output registers. When not registered, it cannot be
asynchronously cleared.
Table 4–3
No error
Single error and fixed
Double error and no fix
Illegal
Illegal
Illegal
Illegal
Table 4–3. Truth Table for ECC Status Flags
shows the truth table for the ECC status flags.
Status
×
64-wide simple dual-port mode. ECC allows you to
eccstatus[2]
RAM Megafunction User
0
0
1
0
0
1
1
eccstatus[1]
0
1
0
0
1
0
1
Altera Corporation
November 2007
Guide.
eccstatus[0]
X
0
1
1
1
0
0