EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 723

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
RCLK output
adder
RCLK PLL
output adder
RCLK input
adder
RCLK PLL input
adder
RCLK output
adder
RCLK PLL
output adder
Table 1–93. EP3SL200 Column Pin Delay Adders for Regional Clock (Part 2 of 2)
Table 1–94. EP3SL200 Row Pin Delay Adders for Regional Clock
Parameter
Parameter
Industrial Commercial V
Industrial
—
—
—
—
—
—
Fast Model
Fast Model
Table 1–94
Regional Clock.
EP3SL340 I/O Timing Parameters
Table 1–95
parameters for EP3SL340 devices for single-ended I/O standards.
-0.011
0.001
Commercial
1.732
1.705
0.014
0.08
specifies EP3SL200 Row Pin delay adders when using the
through
Stratix III Device Datasheet: DC and Switching Characteristics
CCL
0.061
0.073
-2
=1.1V V
V
CCL
2.533
0.191
0.105
Table 1–98
2.64
-2
=1.1V
CCL
0.138
0.134
-3
=1.1V V
V
show the maximum I/O timing
CCL
2.928
2.776
0.151
0.064
-3
=1.1V
CCL
Stratix III Device Handbook, Volume 2
0.227
0.223
-4
=1.1V V
V
CCL
3.175
3.036
0.392
0.268
-4
=1.1V
CCL
0.184
0.18
=1.1V V
V
-4L
CCL
3.041
2.902
0.322
0.103
-4L
=1.1V
CCL
0.399
0.393
=0.9V
1–211
Units
Units
ns
ns
ns
ns
ns
ns