EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 599

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V
LVTTL
Standard
Table 1–53. EP3SL50 Column Pin Delay Adders for Regional Clock
Table 1–54. EP3SL50 Row Pin Delay Adders for Regional Clock
Table 1–55. EP3SL70 Column Pins Input Timing Parameters (Part 1 of 4)
I/O
Parameter
Parameter
GCLK
GCLK
Clock
PLL
Parameter
t
t
t
t
SU
SU
H
H
Table 1–54
Regional Clock.
EP3SL70 I/O Timing Parameters
Table 1–55
parameters for EP3SL70 devices for single-ended I/O standards.
Table 1–55
single-ended I/O standards.
Industrial
Industrial
—
—
—
—
—
—
Industrial Commercial
—
—
—
—
Fast Model
Fast Model
Fast Model
specifies EP3SL50 Row Pin delay adders when using the
through
specifies EP3SL70 Column Pins Input Timing parameters for
Stratix III Device Datasheet: DC and Switching Characteristics
Commercial
Commercial
-0.076
-0.015
-0.033
1.739
1.759
-0.702
-0.336
0.810
0.444
0.01
Table 1–58
-1.018 -1.087 -1.177 -1.129 -1.412
-0.679 -0.804 -0.915 -0.863 -0.756
V
1.160
0.821
1.1V
-0.026 0.043
V
2.699
2.667
0.066
CCL
0.045
0.092
V
-2
1.1V
1.1V
show the maximum I/O timing
CCL
CCL
-2
-2
=
=
=
1.248
0.965
V
1.1V
Stratix III Device Handbook, Volume 2
V
2.975
2.931
0.144
CCL
1.1V
V
0.123
0.162
-3
1.1V
CCL
-3
CCL
-3
=
=
=
V
1.352
1.090
1.1V
V
3.256
3.209
0.126
0.226
1.1V
CCL
0.241
0.255
V
-4
1.1V
CCL
-4
CCL
-4
=
=
=
1.296
1.030
V
1.1V
V
3.034
3.064
0.098
0.187
1.1V
CCL
-4L
V
0.197
CCL
1.1V
0.22
CCL
=
=
-4L
=
-4L
V
1.573
0.917
V
2.937
2.902
0.423
0.9V
0.9V
0.32
-4L
CCL
0.419
CCL
V
0.9V
0.38
CCL
=
=
=
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
1–87
ns
ns