EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 79

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 4–1. Stratix III Byte Enable Functional Waveform
Altera Corporation
November 2007
current data: q (asynch)
don't care: q (asynch)
contents at a0
contents at a1
contents at a2
address
byteena
inclock
wren
data
XXXX
XX
an
FFFF
doutn
doutn
FFFF
Packed Mode Support
Stratix III M9K and M144K blocks support packed mode. The packed
mode feature packs two independent single-port RAMs into one memory
block. The Quartus II software automatically implements packed mode
where appropriate by placing the physical RAM block into true dual-port
mode and using the most significant bit (MSB) of the address to
distinguish between the two logical RAMs. The size of each independent
single-port RAM must not exceed half of the target block size.
Address Clock Enable Support
All Stratix III memory blocks support address clock enable, which holds
the previous address value for as long as the signal is enabled
(addressstall = 1). When the memory blocks are configured in
dual-port mode, each port has its own independent address clock enable.
The default value for the address clock enable signals is low (disabled).
10
a0
FFFF
ABXX
ABFF
ABCD
01
a1
TriMatrix Embedded Memory Blocks in Stratix III Devices
XXCD
FFCD
11
a2
ABCD
ABCD
ABFF
Stratix III Device Handbook, Volume 1
a0
FFCD
ABFF
ABFF
ABCD
a1
XXXX
XX
FFCD
FFCD
a2
ABCD
ABCD
4–5