EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 157

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
The sub-regional clock scheme allows the formation of independent
sub-regional clock regions for optimal and efficient use of global and
regional clock resources. You can partition the device into a maximum of
16 sub-regional clock regions. Each region is driven by a global or
regional clock or by an adjacent ALM. This technique allows the
formation of optimally sized synchronous clock regions for the best
utilization of clock network resources.
that you can divide the device into 16, 8, or 12 independent sub-regions.
Figure 6–6. Sixteen Independent Sub-Regional Clock Regions
Figure 6–7. Eight Independent Sub-Regional + One Dual-Regional Clock
Region
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
Figures
6–6, 6–7, and
6–8
show
6–7