EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 602

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EP3SE50F780I3N

Manufacturer Part Number
EP3SE50F780I3N
Description
Stratix III
Manufacturer
Altera
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0
I/O Timing
1–90
Stratix III Device Handbook, Volume 2
1.5-V
HSTL
CLASS II
1.2-V
HSTL
CLASS I
1.2-V
HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
3.3-V
LVTTL
Standard
Standard
Table 1–55. EP3SL70 Column Pins Input Timing Parameters (Part 4 of 4)
Table 1–56. EP3SL70 Row Pins Input Timing Parameters (Part 1 of 4)
I/O
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
Clock
PLL
PLL
PLL
PLL
PLL
PLL
Parameter
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SU
SU
SU
SU
SU
SU
SU
SU
SU
SU
SU
SU
H
H
H
H
H
H
H
H
H
Table 1–56
single-ended I/O standards.
Industrial Commercial
Industrial Commercial
Fast Model
Fast Model
specifies EP3SL70 Row Pins Input Timing parameters for
-0.539
-0.495
-0.532
-0.502
-0.532
-0.502
-0.702
-0.336
-0.702
-0.336
-0.702
-0.336
0.607
0.614
0.614
0.810
0.444
0.810
0.444
0.810
0.444
-1.018 -1.087 -1.177 -1.129 -1.412
-0.679 -0.804 -0.915 -0.863 -0.756
-0.688 -0.703 -0.786 -0.740 -1.027
-1.004 -1.182 -1.298 -1.245 -1.134
-0.673 -0.687 -0.770 -0.724 -1.011
-1.018 -1.198 -1.314 -1.261 -1.150
-0.673 -0.687 -0.770 -0.724 -1.011
-1.018 -1.198 -1.314 -1.261 -1.150
-1.018 -1.087 -1.177 -1.129 -1.412
-0.679 -0.804 -0.915 -0.863 -0.756
-1.018 -1.087 -1.177 -1.129 -1.412
-0.679 -0.804 -0.915 -0.863 -0.756
V
1.160
0.821
V
1.151
1.166
1.166
1.160
0.821
1.160
0.821
1.1V
1.1V
CCL
CCL
-2
-2
=
=
V
1.248
0.965
1.349
1.365
1.365
1.248
0.965
1.248
0.965
1.1V
V
1.1V
CCL
-3
CCL
-3
=
=
V
1.352
1.090
1.1V
V
1.481
1.497
1.497
1.352
1.090
1.352
1.090
1.1V
CCL
-4
CCL
-4
=
=
V
1.296
1.030
1.1V
1.419
1.435
1.435
1.296
1.030
1.296
1.030
V
CCL
1.1V
CCL
=
Altera Corporation
-4L
=
-4L
V
1.573
0.917
November 2007
0.9V
CCL
V
1.302
1.318
1.318
1.573
0.917
1.573
0.917
0.9V
CCL
=
=
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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