EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 213

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–41. Dynamic Phase Shifting Waveform
Altera Corporation
November 2007
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
a
b
Dynamic phase-shifting can be repeated indefinitely. All signals are
synchronous to scanclk and must meet t
to scanclk edges.
The phasestep signal is latched on the negative edge of scanclk. In
Figure
phasestep must stay high for at least two scanclk cycles. On the
second scanclk rising edge after phasestep is latched (the fourth
scanclk rising edge in
phasecounterselect are latched and the PLL starts dynamic phase-
shifting for the specified counter(s) and in the indicated direction. On the
fourth scanclk rising edge, phasedone goes high to low and remains
low until the PLL finishes dynamic phase-shifting. You can perform
another dynamic phase-shift after the phasedone signal goes from low
to high.
Depending on the VCO and scanclk frequencies, phasedone low time
may be greater than or less than one scanclk cycle. The maximum time
for reconfiguring phase shift dynamically is to be determined (TBD)
based on device characterization.
PHASEDONE goes low synchronous with SCANCLK
6–41, this is shown by the second scanclk falling edge.
Figure
Clock Networks and PLLs in Stratix III Devices
6–41), the values of phaseupdown and
c
Stratix III Device Handbook, Volume 1
d
su
/t
h
requirements with respect
6–63