EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 406

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

JTAG Configuration
11–46
Stratix III Device Handbook, Volume 1
If CONF_DONE is high, the software indicates that configuration was
successful. After the configuration bitstream is transmitted serially via
the JTAG TDI port, the TCK port is clocked an additional 1,094 cycles to
perform device initialization.
Stratix III devices have dedicated JTAG pins that always function as
JTAG pins. Not only can you perform JTAG testing on Stratix III devices
before and after, but also during configuration. While other device
families do not support JTAG testing during configuration, Stratix III
devices support the bypass, id code, and sample instructions during
configuration without interrupting configuration. All other JTAG
instructions may only be issued by first interrupting configuration and
reprogramming I/O pins using the CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured via the
JTAG port and when issued, interrupts configuration. This instruction
allows you to perform board-level testing prior to configuring the
Stratix III device or waiting for a configuration device to complete
configuration. Once configuration has been interrupted and JTAG testing
is complete, you must reconfigure the part via JTAG (PULSE_CONFIG
instruction) or by pulsing nCONFIG low.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE)
pins on Stratix III devices do not affect JTAG boundary-scan or
programming operations. Toggling these pins does not affect JTAG
operations (other than the usual boundary-scan operation).
When designing a board for JTAG configuration of Stratix III devices,
consider the dedicated configuration pins.
pins should be connected during JTAG configuration.
nCE
nCEO
MSEL
Table 11–12. Dedicated Configuration Pin Connections During JTAG
Configuration (Part 1 of 2)
Signal
On all Stratix III devices in the chain,
by connecting it to ground, pulling it low via a resistor, or driving
it by some control circuitry. For devices that are also in
multi-device FPP, AS, or PS configuration chains, the
should be connected to GND during JTAG configuration or JTAG
configured in the same order as the configuration chain.
On all Stratix III devices in the chain, you can leave
or connected to the
These pins must not be left floating. These pins support
whichever non-JTAG configuration is used in production. If you
only use JTAG configuration, tie these pins to ground.
nCE
of the next device.
Description
Table 11–12
nCE
should be driven low
Altera Corporation
shows how these
November 2007
nCEO
nCE
floating
pins