EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 494

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III Power Technology
16–4
Stratix III Device Handbook, Volume 1
Note to
(1)
LAB
Routing
Memory Blocks
DSP Blocks
Global Clock Networks
I/O Elements
Table 16–1. Stratix III Programmable Power Capabilities
Tiles with DSP blocks, memory blocks, and I/O elements that are used in the design are always set to the
high-speed mode. Unused DSP blocks, memory blocks, and I/O interfaces are set to low-power mode by default.
Table
16–1:
The Quartus II software can set unshared inputs and unused device
resources in the design in low-power mode to reduce static and dynamic
power. The Quartus II software can set the following resources to low
power when they are not used in the design:
■
■
■
■
■
■
If the PLL is instantiated in the design, asserting a reset high keeps the
PLL in low power.
Relationship Between Selectable Core Voltage and
Programmable Power Technology
Table 16–1
Speed grade considerations can add to the permutations to give you
flexibility in designing your system.
Selectable Core Voltage
LABs and MLABs
TriMatrix memory blocks
External memory interface circuitry
DSP blocks
PLL
SERDES and DPA blocks
shows available Stratix III programmable power capabilities.
Yes
Yes
Yes
Yes
Yes
No
Programmable Power Technology
Fixed setting
Fixed setting
Fixed setting
Yes
Yes
No
Altera Corporation
(1)
(1)
(1)
October 2007