EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 118

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Operational Mode Descriptions
Operational
Mode
Descriptions
5–18
Stratix III Device Handbook, Volume 1
Depending on the configuration, the chainout results can be routed to the
input of the next half-block’s chainout adder input or to the general fabric
(functioning as regular output registers). Refer to
Descriptions” on page 5–18
The second-stage and output registers are triggered by the positive edge
of the clock signal and are cleared on power up. The following DSP block
signals control the output registers within the DSP block:
■
■
■
Independent Multiplier Modes
In independent input and output multiplier mode, the DSP block
performs individual multiplication operations for general-purpose
multipliers.
9-, 12- and 18-Bit Multiplier
You can configure each DSP block multiplier for 9-, 12-, or 18-bit
multiplication. A single DSP block can support up to eight individual
9 × 9 multipliers, six 12 × 12 multipliers, or up to four individual 18 × 18
multipliers. For operand widths up to 9 bits, a 9 × 9 multiplier is
implemented. For operand widths from 10 to 12 bits, a 12 × 12 multiplier
is implemented, and for operand widths from 13 to 18 bits, an 18 × 18
multiplier is implemented. This is done by the Quartus II software by
zero-padding the LSBs.
the independent multiplier operation mode.
clock[3..0]
ena[3..0]
aclr[3..0]
Figures
for details.
5–8, 5–9, and
5–10
“Operational Mode
show the DSP block in
Altera Corporation
October 2007